3D Integration & Advanced Packaging Workshop
Workshop Overview
Chair/Co-Chair:
Time & Venue:
9:00 – 12:30, 22 May 2024 (Wednesday), at room Virgo 4
Abstract/Information:
As CMOS process advancements slow down, the chiplet design approach and its associated technologies have garnered significant attention due to their potential for improving manufacturing yield, reducing costs and offering extensible SOC architecture. This however will require radical shifts in chip design methodologies. This session will examine the latest developments in chiplet technology, encompassing SOC architectures built upon chiplet frameworks, chiplet interface circuits (such as D2D interconnect technology), chiplet EDA tools, and cutting-edge packaging techniques tailored for chiplet integration. We will also discuss the challenges impacting chiplet technology, including varying standards, complexities in designing, testing and thermal management of chipletbased implementation.
Time | Title | Speaker |
---|---|---|
9:00 – 9:22 | Embracing a New Chapter for 3D IC Design with Generative AI: Optimize from Architecture Conceptual Level to Signoff |
Erick Chao, Senior Software Architect, Cadence Design Systems, Inc |
9:22 – 9:45 | Chiplet Interface Circuit Design Challenge and Standards Development | Qinfen Hao, President, Wuxi Institute of Interconnect Technology, Co. Ltd., China |
9:45 – 10:07 | Opportunities and Challenges in general purpose CPU design based on chiplet architecture |
William Fan, CEO, M2 Semiconductor Ltd., China |
10:07 – 10:30 | Heterogeneous Chiplet Integration Technologies for AI Driven Accelerated Computing |
Surya Bhattacharya, SiP Director, Institute of Microelectronics, A*STAR, Singapore |
10:30 – 11:00 | Tea Break | |
11:00 – 11:22 | Computing: The Power of Die-to-Die Interfaces and Chiplet Architecture | Yu Wang, Sr. Analog Design Manager, Kiwimoore, Semiconductor Co. Ltd, Shanghai, China |
11:22 – 11:45 | Signal/Power Integrity and Multiphysics Analysis for Interconnects of Chiplet |
Bo Pu, Vice President, Ningbo DeTooLIC Technology Co., Ltd, Ningbo, Zhejiang, China |
11:45 – 12:07 | Opportunities and challenges faced by advanced chiplet interconnection technology |
Shujuan Liu, Engineer, Hubei Yangtze Laboratories, China |
12:07 – 12:30 | Radiative cooling via the integration of heat spreader and radiator in electronic device |
Siah Chun Fei, Research Fellow, National University of Singapore, Singapore |
12:30 – 13:30 | Lunch |